1. Field of the Invention
The invention relates to a semiconductor memory device, and particularly to a semiconductor memory device having an address transition detection circuit and a method for operating the same.
2. Description of the Prior Art
FIG. 10 is a block diagram showing a conventional mask ROM (read only memory) having an address transition detection circuit. On a semiconductor chip 1a, there are provided a memory matrix 2, an address input circuit 3, a row decoder 4, a column decoder 5, a sense circuit 6, an output circuit 7 and an address transition detection circuit 8a.
Memory matrix 2 includes a plurality of word lines, a plurality of bit lines intersecting the word lines, and a plurality of memory cells arranged at intersections of the word lines and the bit lines. FIG. 10 shows only one word line WL, one bit line BL and one memory cell MC.
Address input circuit 3 receives externally applied address signals a0-an, and applies the same to address transition detection circuit 8a. Address input circuit 3 also applies a row address signal and a column address signal to row decoder 4 and column decoder 5, respectively. Row decoder 4 is responsive to the row address signal to select any of word lines WL in memory matrix 2. Data is read from memory cells MC connected to word line WL thus selected to corresponding bit line BL.
Sense circuit 6 includes a selection circuit which is responsive to the column address signal to select any of data read to bit lines BL, a precharging circuit which precharges bit lines BL in memory matrix 2, a sense amplifier circuit which senses and amplifies the data, and a latch circuit which holds the output data. Output circuit 7 externally outputs the data applied from sense circuit 6 as output data D.sub.out.
Address transition detection circuit 8a detects the transition of address signal to generate an address transition detection signal ATD in a pulse form. In response to detection signal ATD, sense circuit 6 precharges bit line BL, performs sensing and amplifying of data, and holds the output data.
In this manner, sense circuit 6 is controlled in response to detection signal ATD applied from address transition detection circuit 8a.
As shown in FIG. 11, however, if address transition detection circuit 8a generates detection signal ATD in the pulse form immediately after the application of power, and particularly before supply voltage Vcc reaches a predetermined voltage V1 which allows a stable operation of sense circuit 6, sense circuit 6 malfunctions. In order to prevent the malfunction, a dummy cycle must be provided in the address signal by setting a chip enable signal CE at an inactive state (high level) immediately after the application of power.